1. Field of the Invention
The present invention relates to metal adhesion in back side metal (BSM), as used, for example, in 3D chip integration and to the electrically interconnecting via structures, such as, Thru-Silicon-Via (TSV) structures used to carry electrical signals vertically through the semiconductor die. More particularly, the present invention relates to the BSM contact made to the semiconductor wafer and the exposed TSV structures extending to the bottom of the wafer.
2. Background and Related Art
In the packaging of electronic devices, such as, semiconductor chips and wafers, or semiconductor chip carriers, vertical interconnection to the next packaging level, whether it be a chip carrier or chip, may be achieved by Thru-Silicon-Vias (TSV). One prior art approach to creating conductive vias in semiconductor material, such as a silicon semiconductor wafer, is to use what might be called a “via first” approach. The general steps in such an approach are etching the vias, forming insulation layers on the via walls and metallization. When a “blind via” approach is used, the vias are not etch through the wafer so that a “thru-via” is rendered only after the carrier is suitably thinned to expose the via bottoms. An example of such an approach may be found in U.S. Pat. No. 5,998,292. FIGS. 1A-F, as described herein, generally disclose a process that may be used in the “blind via” approach.
One of the difficulties encountered in forming the back side metallurgy that makes electrical contact with the via exposed after thinning is forming reliable electrical contact structure. Reliable electrical contact structures often require multiple layers of metal to be formed at the wafer level. For example, one layer is used to provide good adhesion to the back side of the wafer and via, a second layer may be used on top of the adhesion layer to provide good conductivity and a third layer may be used as a barrier layer against diffusion of the second layer to the surface. A fourth layer may be used for oxidation/corrosion prevention. It is clear, however, that other multilayer metallurgy arrangements may be used to form BSM layer.
However, it has been found that after the wafer is diced into chips, the BSM layer tends to delaminate from the semiconductor material, such as, silicon, at the chip edges. Such delamination at the chip edges may be on the order of 1 mm which creates serious reliability problems considering the typical chip size is on the order of millimeters.
It has also been found that chip dicing induced delamination is substantially reduced, if not eliminated, where the BSM is deposited after wafer grinding without going though polishing process steps first. It is thus thought that the surface roughness resulting from the wafer grinding process promotes adhesion between the silicon surface and BSM layer.
On the other hand, it is understood that a rough BSM/TSV interface at the bottom of the TSV may create mechanical and ohmic contact integrity problems which will affect electrical performance and reliability of the TSV interconnection structure.